1. Field of the Invention
The present invention relates to a display device and method of driving the same, and more particularly, to a display device having a source drive integrated circuit (or data driver) with improved reliability.
2. Discussion of the Related Art
A display device typically includes a plurality of source drive integrated circuits (hereinafter, “ICs”) for supplying data voltages to the data lines of a display panel, a plurality of gate drive ICs for sequentially supplying a gate pulse (or scan pulse) to the gate lines of the display panel, and a timing controller for controlling the source and gate drive ICs.
The timing controller supplies digital video data, a clock for sampling the digital video data, a control signal for controlling an operation of the source drive ICs, and the like, to the source drive ICs through an interface such as a mini low-voltage differential signaling (LVDS) interface. The source drive ICs converts the digital video data input from the timing controller into analog data voltages and supply them to the data lines.
When connecting the timing controller and the source drive ICs in a multi-drop manner through the mini LVDS interface, many signal lines including R data transmission lines, G data transmission lines, B data transmission lines, control lines for controlling the operation timing of output and polarity conversion of the source drive ICs, clock transmission lines, etc. are required between the timing controller and the source drive ICs.
In RGB data transmission, for example, RGB digital video data and a clock are each transmitted in differential signal pairs through the mini-LVDS interface. As a result, when odd data and even data are simultaneously transmitted, at least 14 signal lines may be needed between the timing controller and the source driver ICs for the transmission of the RGB data. If RGB data is a 10-bit data, 18 signal lines may be needed. Thus, many signal lines are to be formed on a source printed circuit board (PCB) mounted between the timing controller and the source drive ICs, which may make it difficult to reduce the width of the source PCB.
The present applicant proposed a new data transmission protocol (hereinafter, referred to as “Embedded Panel Interface (EPI) protocol”) for connecting a timing controller and source driver ICs in a point-to-point manner to reduce or minimize the number of signal lines between the timing controller and the source driver ICs and to stabilize signal transmission in Korean Patent Application No. 10-2008-0127458 (filed on Dec. 15, 2008), U.S. patent application Ser. No. 12/543,996 (field on Aug. 19, 2009), Korean Patent Application No. 10-2008-0127456 (filed on Dec. 15, 2008), U.S. patent application Ser. No. 12/461,652 (field on Aug. 19, 2009), Korean Patent Application No. 10-2008-0132466 (filed on Dec. 23, 2008), and U.S. patent application Ser. No. 12/547,341 (field on Aug. 7, 2009).
The EPI protocol may satisfy the following interface regulations (1) to (3).
(1) A transmitting terminal of the timing controller is connected to receiving terminals of the source driver ICs via data line pairs in a point-to-point manner without sharing the lines. (2) No separate clock line pairs are connected between the timing controller and the source driver ICs. The timing controller transmits video data and control data, each along with a clock signal, to the source driver ICs via the data line pairs. (3) A clock recovery circuit for clock and data recovery (CDR) is embedded in each of the source driver ICs. The timing controller transmits a clock training pattern signal or a preamble signal to the source driver ICs so that then the phase and frequency of the output of the clock recovery circuit should be locked. When the clock training pattern signal and the clock signal are input via the data line pairs, the clock recovery circuits embedded in the source drive ICs generate internal clocks.
When the phase and frequency of each internal clock are locked, the source driver ICs feed a lock signal LOCK of a high logic level indicating a stabilized output back as an input to the timing controller. The lock signal LOCK is fed back as an input to the timing controller through a lock feedback signal line connected to the timing controller and the last source driver IC.
In the EPI protocol, the timing controller transmits the clock training pattern signal to the source drive ICs before transmitting control data and video data of an input image. The clock recovery circuit of one of the source drive ICs outputs an internal clock based on the clock training pattern signal to recover the clock and perform a clock training operation. When the phase and frequency of the internal clock are stably locked, the clock recovery circuit of the source drive IC and the timing controller establish a data link. After establishing a data link with the timing controller, the source drive IC sends the lock signal LOCK to the next source drive IC. The timing controller starts to transmit the control data and the video data to the source drive ICs in response to the lock signal LOCK received from the last source drive IC.
In this procedure, the lock signal LOCK may not be sent to the next source drive IC when there is an abnormality or malfunction in the source drive IC. As a result, the lock signal LOCK does not make it to the timing controller, and the timing controller cannot thus supply a data voltage to the source drive ICs.
Recently, a method of supplying data voltages simultaneously to both ends of the data lines has been used in order to make up for a data voltage drop which may occur due to the longer distance between the source drive ICs and the data lines during the supply of the data voltages to a large-sized display panel. That is, first source drive ICs are electrically connected to one end of the data lines, while second source drive ICs are electrically connected to the other end of the data lines. Thus, the first and second source drive ICs simultaneously supply the data voltages to the data lines.
In the EPI protocol, when some of the first and second source drive ICs fail to establish data links with the timing controller, they may not supply the data voltages to the data lines. On the other hand, normally operating source drive ICs supply the data voltages to those data lines from the other side of the data lines. As a result, as the data lines receive the data voltages from the normally operating source drive ICs, the malfunctioning source drive ICs formed at the other end of the data lines may be burned by a sink current.